// Send packet with false leader sequence (DPhy CTS 2.4.3)

// send HS burst entry on active lanes
# LP_STATES ACT
3 1 0

// send false leader sequence on active lanes
# HS_BYTES ACT
2eh

// send HSZero for 200 ns
# HS_ZERO ACT 200

// send HS sync on active lanes
# HS_BYTES ACT
b8h

// send generic long write packet
# HS_BYTES DEMUX
29h -4 -1 1 2 3 4 5 -2

// end HS burst
# HS_BURST_EXIT